"Lunch & Learn: SystemVerilog Meets Emulation"
Verifying SOCs and ASICs requires an exponentially growing number of simulation cycles, especially now that software is an integral part of the design. That need has pushed many designers to FPGA prototyping and emulation, but traditional in-circuit target boards are showing their age.
In this one-hour technical presentation and demo, we show the latest advance in efficient testbench methodology: hardware transactors. Learn how a behavioral SystemVerilog compiler can automatically generate hardware-friendly transactors. Those transactors are the key components that connect your existing simulation environment to an extremely fast emulation of your design. By reusing this behavioral SystemVerilog coding style, you improve your time-to-prototype and reduce your risk to miss a critical bug at tape-out
Register Today
Sessions take place directly at your site over the lunch hour (and include food!) to accomodate your busy schedule.
Schedule your Lunch & Learn session today: sales@eve-team.com or visit our contact page